We’re adding support for the i.MXRT1180 in the imxrt-rs project, and we’d like to re-use as many drivers as we can from imxrt-hal. The SVDs for the 1180 describe differences in the LPSPI, LPI2C, and LPUART peripherals. How does that affect the drivers we’re using on other i.MXRT MCUs?

In general, these three peripherals have additional registers to support DMA bursting. There are also new read-only data registers for accessing FIFOs. The designers introduced these registers in reserved memory. We can safely ignore these.

When I note a reference manual (RM) difference, I’m comparing against the 1170 RM, revision 2.

LPSPI

The RT1180 RM documents a major revision update for this peripheral. We have a new clock configuration register, CCR1, adjacent to the usual CCR. The extra fields in CCR1 provide more control over SCK and PCS timing. But, they’re optional; writes to the usual fields in CCR will propagate into CCR1. The RM says this behaivor is “backwards compatible.”

The catch: half of CCR’s fields are now write-only, read as zero (WO/RAZ). If we try to read-modify-write (RMW) the register, we’ll read invalid values. To maintain compatibility, our driver could cache the WO/RAZ fields in memory. There’s other tricks we could play by evaluating the version number at runtime, build-time feature flags, etc. but I don’t think we need those.

There are some new fields in configuration registers. We should already be RMWing those registers.

LPI2C

The RM documents the same major revision and an increased minor revision. There are new registers for configuring I2C target functions. The imxrt-hal driver only supports I2C controllers, not targets. We can evaluate these later.

The FIFO capacities are twice as large as the FIFOs on the other i.MXRT MCUs. Although increasing FIFO sizes isn’t breaking, our software driver shouldn’t assume any constant FIFO sizes; we should extract sizes from PARAM. (This applies throughout our drivers; I know I’ve been lazy and put a constant or two somewhere…)

Again, there are new fields in configuration registers. We should be RMWing those.

LPUART

The RM documents the same major revision and an increased minor revision. The feature set bitmask indicates we now support “enhanced” feature sets. We see this in all the new registers added at the end of the memory map.

The FIFO capacities are 4x larger. Assuming a smaller FIFO isn’t harmful, but it would be nice to take advantage of this larger size.

STAT gains new RW configuration bits. Since STAT has always had configuration bits, we should be accounting for this possibility.